#define IA32_P5_MC_ADDR 0x00000000
#define IA32_P5_MC_TYPE 0x00000001
#define IA32_MONITOR_FILTER_SIZE 0x00000006
#define IA32_TIME_STAMP_COUNTER 0x00000010
#define IA32_PLATFORM_ID 0x00000017
#define IA32_APIC_BASE 0x00000018
#define IA32_FEATURE_CONTROL 0x0000003A
#define IA32_TSC_ADJUST 0x0000003B
#define IA32_SPEC_CTRL 0x00000048
#define IA32_PRED_CMD 0x00000049
#define IA32_BIOS_UPDT_TRIG 0x00000079
#define IA32_BIOS_SIGN_ID 0x0000008B
#define IA32_SGXLEPUPKEYHASH0 0x0000008C
#define IA32_SGXLEPUBKEYHASH1 0x0000008D
#define IA32_SGXLEPUBKEYHASH2 0x0000008E
#define IA32_SGXLEPUBKEYHASH3 0x0000008F
#define IA32_SMM_MONITOR_CTL 0x0000009B
#define IA32_SMBASE 0x0000009E
#define IA32_PMC0 0x000000C1
#define IA32_PMC1 0x000000C2
#define IA32_PMC2 0x000000C3
#define IA32_PMC3 0x000000C4
#define IA32_PMC4 0x000000C5
#define IA32_PMC5 0x000000C6
#define IA32_PMC6 0x000000C7
#define IA32_PMC7 0x000000C8
#define IA32_CORE_CAPABILITIES 0x000000CF
#define IA32_UMWAIT_CONTROL 0x000000E1
#define IA32_MPERF 0x000000E7
#define IA32_APERF 0x000000E8
#define IA32_MTRRCAP 0x000000FE
#define IA32_ARCH_CAPABILITIES 0x0000010A
#define IA32_FLUSH_CMD 0x0000010B
#define IA32_TSX_CTRL 0x00000122
#define IA32_SYSENTER_CS 0x00000174
#define IA32_SYSENTER_ESP 0x00000175
#define IA32_SYSENTER_EIP 0x00000176
#define IA32_MCG_CAP 0x00000179
#define IA32_MCG_STATUS 0x0000017A
#define IA32_MCG_CTL 0x0000017B
#define IA32_PERFEVTSEL0 0x00000186
#define IA32_PERFEVTSEL1 0x00000187
#define IA32_PERFEVTSEL2 0x00000188
#define IA32_PERFEVTSEL3 0x00000189
#define IA32_PERF_STATUS 0x00000198
#define IA32_PERF_CTL 0x00000199
#define IA32_CLOCK_MODULATION 0x0000019A
#define IA32_THERM_INTERRUPT 0x0000019B
#define IA32_THERM_STATUS 0x0000019C
#define IA32_MISC_ENABLE 0x000001A0
#define IA32_ENERGY_PERF_BIAS 0x000001B0
#define IA32_PACKAGE_THERM_STATUS 0x000001B1
#define IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
#define IA32_DEBUG_CTL 0x000001D9
#define IA32_SMRR_PHYSBASE 0x000001F2
#define IA32_SMRR_PHYSMASK 0x000001F3
#define IA32_PLATFORM_DCA_CAP 0x000001F8
#define IA32_CPU_DCA_CAP 0x000001F9
#define IA32_DCA_0_CAP 0x000001FA
#define IA32_MTRR_PHYSBASE0 0x00000200
#define IA32_MTRR_PHYSMASK0 0x00000201
#define IA32_MTRR_PHYSBASE1 0x00000202
#define IA32_MTRR_PHYSMASK1 0x00000203
#define IA32_MTRR_PHYSBASE2 0x00000204
#define IA32_MTRR_PHYSMASK2 0x00000205
#define IA32_MTRR_PHYSBASE3 0x00000206
#define IA32_MTRR_PHYSMASK3 0x00000207
#define IA32_MTRR_PHYSBASE4 0x00000208
#define IA32_MTRR_PHYSMASK4 0x00000209
#define IA32_MTRR_PHYSBASE5 0x0000020A
#define IA32_MTRR_PHYSMASK5 0x0000020B
#define IA32_MTRR_PHYSBASE6 0x0000020C
#define IA32_MTRR_PHYSMASK6 0x0000020D
#define IA32_MTRR_PHYSBASE7 0x0000020E
#define IA32_MTRR_PHYSMASK7 0x0000020F
#define IA32_MTRR_PHYSBASE8 0x00000210
#define IA32_MTRR_PHYSMASK8 0x00000211
#define IA32_MTRR_PHYSBASE9 0x00000212
#define IA32_MTRR_PHYSMASK9 0x00000213
#define IA32_MTRR_FIX64K_00000 0x00000250
